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| author | Matthias Braun <matze@braunis.de> | 2016-03-01 20:03:21 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-03-01 20:03:21 +0000 |
| commit | 17cb57995eb9535c30cdff864b6157a34d1f5143 (patch) | |
| tree | b3f0a74bf54273a3ceba97c71bec0daaa24cdd5f /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | 8e0a734fc5ee45e2dc8926c58b6ed68fd57500ea (diff) | |
| download | llvm-17cb57995eb9535c30cdff864b6157a34d1f5143.zip llvm-17cb57995eb9535c30cdff864b6157a34d1f5143.tar.gz llvm-17cb57995eb9535c30cdff864b6157a34d1f5143.tar.bz2 | |
TableGen: Check scheduling models for completeness
TableGen checks at compiletime that for scheduling models with
"CompleteModel = 1" one of the following holds:
- Is marked with the hasNoSchedulingInfo flag
- The instruction is a subclass of Sched
- There are InstRW definitions in the scheduling model
Typical steps necessary to complete a model:
- Ensure all pseudo instructions that are expanded before machine
scheduling (usually everything handled with EmitYYY() functions in
XXXTargetLowering).
- If a CPU does not support some instructions mark the corresponding
resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }".
- Add missing scheduling information.
Differential Revision: http://reviews.llvm.org/D17747
llvm-svn: 262384
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions