Extract LaneBitmask into a separate type

Specifically avoid implicit conversions from/to integral types to
avoid potential errors when changing the underlying type. For example,
a typical initialization of a "full" mask was "LaneMask = ~0u", which
would result in a value of 0x00000000FFFFFFFF if the type was extended
to uint64_t.

Differential Revision: https://reviews.llvm.org/D27454

llvm-svn: 289820

1 files changed, 8 insertions, 8 deletions

diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp
index 963b04b..04052b7 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.cpp
+++ b/llvm/lib/Target/Hexagon/RDFGraph.cpp
@@ -30,7 +30,7 @@ namespace llvm {
 namespace rdf {
 
 raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P) {
-  if (P.Mask != ~LaneBitmask(0))
+  if (!P.Mask.all())
     OS << ':' << PrintLaneMask(P.Mask);
   return OS;
 }
@@ -662,7 +662,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
   RegisterRef NR = normalize(RR);
   auto F = Masks.find(NR.Reg);
   if (F != Masks.end()) {
-    if (F->second & NR.Mask)
+    if (!(F->second & NR.Mask).none())
       return true;
   }
   if (CheckUnits) {
@@ -676,7 +676,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
 bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
   // Always have a cover for empty lane mask.
   RegisterRef NR = normalize(RR);
-  if (!NR.Mask)
+  if (NR.Mask.none())
     return true;
   auto F = Masks.find(NR.Reg);
   if (F == Masks.end())
@@ -717,7 +717,7 @@ RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
   if (F == Masks.end())
     return *this;
   LaneBitmask NewM = F->second & ~NR.Mask;
-  if (NewM == LaneBitmask(0))
+  if (NewM.none())
     Masks.erase(F);
   else
     F->second = NewM;
@@ -1089,7 +1089,7 @@ RegisterRef DataFlowGraph::normalizeRef(RegisterRef RR) const {
 RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
   if (AR.Reg == BR.Reg) {
     LaneBitmask M = AR.Mask & BR.Mask;
-    return M ? RegisterRef(AR.Reg, M) : RegisterRef();
+    return !M.none() ? RegisterRef(AR.Reg, M) : RegisterRef();
   }
 #ifndef NDEBUG
   RegisterRef NAR = normalizeRef(AR);
@@ -1211,7 +1211,7 @@ bool DataFlowGraph::alias(RegisterRef RA, RegisterRef RB) const {
       // This can happen when the register has only one unit, or when the
       // unit corresponds to explicit aliasing. In such cases, the lane mask
       // from RegisterRef should be ignored.
-      if (!PA.second || !PB.second)
+      if (PA.second.none() || PB.second.none())
         return true;
 
       // At this point the common unit corresponds to a subregister. The lane
@@ -1221,7 +1221,7 @@ bool DataFlowGraph::alias(RegisterRef RA, RegisterRef RB) const {
       // while the lane mask of r2 in d1 may be 0b0001.
       LaneBitmask LA = PA.second & RA.Mask;
       LaneBitmask LB = PB.second & RB.Mask;
-      if (LA != 0 && LB != 0) {
+      if (!LA.none() && !LB.none()) {
         unsigned Root = *MCRegUnitRootIterator(PA.first, &TRI);
         // If register units were guaranteed to only have 1 bit in any lane
         // mask, the code below would not be necessary. This is because LA
@@ -1232,7 +1232,7 @@ bool DataFlowGraph::alias(RegisterRef RA, RegisterRef RB) const {
         const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(Root);
         LaneBitmask MaskA = TRI.reverseComposeSubRegIndexLaneMask(SubA, LA);
         LaneBitmask MaskB = TRI.reverseComposeSubRegIndexLaneMask(SubB, LB);
-        if (MaskA & MaskB & RC.LaneMask)
+        if (!(MaskA & MaskB & RC.LaneMask).none())
           return true;
       }