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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-11-18 20:28:11 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-11-18 20:28:11 +0000 |
| commit | efa74e0280b28916b101d4e332b90b472d73172e (patch) | |
| tree | ed6b5aed90af8b0f0d71c31f169307192d46bd6d /llvm/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp | |
| parent | e53e8c8e5888debe378c0cf35fcd4efb03c4af03 (diff) | |
| download | llvm-efa74e0280b28916b101d4e332b90b472d73172e.zip llvm-efa74e0280b28916b101d4e332b90b472d73172e.tar.gz llvm-efa74e0280b28916b101d4e332b90b472d73172e.tar.bz2 | |
[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
Adding test to show correct instruction selection and encoding.
llvm-svn: 222249
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp b/llvm/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp index 34319ee..8ef4c3a 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp @@ -100,7 +100,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::CONST32_Int_Real), HEXAGON_RESERVED_REG_1).addImm(Offset); - BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr), + BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add), HEXAGON_RESERVED_REG_1) .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), @@ -146,7 +146,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::CONST32_Int_Real), HEXAGON_RESERVED_REG_1).addImm(Offset); - BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr), + BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add), HEXAGON_RESERVED_REG_1) .addReg(FP) .addReg(HEXAGON_RESERVED_REG_1); |