diff options
author | Duncan P. N. Exon Smith <dexonsmith@apple.com> | 2016-07-12 01:55:32 +0000 |
---|---|---|
committer | Duncan P. N. Exon Smith <dexonsmith@apple.com> | 2016-07-12 01:55:32 +0000 |
commit | 98226e3d93f6cfbfc93b02ef79a988fcbe20ae38 (patch) | |
tree | 25aabac7d80623761ec657cdd8c37f28ed7f01d5 /llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | |
parent | fdd30c620da25a98c7cae6e413577ac7534fa9e0 (diff) | |
download | llvm-98226e3d93f6cfbfc93b02ef79a988fcbe20ae38.zip llvm-98226e3d93f6cfbfc93b02ef79a988fcbe20ae38.tar.gz llvm-98226e3d93f6cfbfc93b02ef79a988fcbe20ae38.tar.bz2 |
Hexagon: Avoid implicit iterator conversions, NFC
Avoid implicit iterator conversions from MachineInstrBundleIterator to
MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr&
over MachineInstr* and switching to range-based for loops.
There's a long tail of API cleanup here, but I'm planning to leave the
rest to the Hexagon maintainers. HexagonInstrInfo defines many of its
own predicates, and most of them still take MachineInstr*. Some of
those actually check for nullptr, so I didn't feel comfortable changing
them to MachineInstr& en masse.
llvm-svn: 275142
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index 93dd6f8..c8b4a4c 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1318,7 +1318,7 @@ namespace { : Transformation(true), HII(hii), MRI(mri), BT(bt) {} bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override; private: - bool isTfrConst(const MachineInstr *MI) const; + bool isTfrConst(const MachineInstr &MI) const; bool isConst(unsigned R, int64_t &V) const; unsigned genTfrConst(const TargetRegisterClass *RC, int64_t C, MachineBasicBlock &B, MachineBasicBlock::iterator At, DebugLoc &DL); @@ -1346,9 +1346,8 @@ bool ConstGeneration::isConst(unsigned R, int64_t &C) const { return true; } - -bool ConstGeneration::isTfrConst(const MachineInstr *MI) const { - unsigned Opc = MI->getOpcode(); +bool ConstGeneration::isTfrConst(const MachineInstr &MI) const { + unsigned Opc = MI.getOpcode(); switch (Opc) { case Hexagon::A2_combineii: case Hexagon::A4_combineii: @@ -1418,7 +1417,7 @@ bool ConstGeneration::processBlock(MachineBasicBlock &B, const RegisterSet&) { RegisterSet Defs; for (auto I = B.begin(), E = B.end(); I != E; ++I) { - if (isTfrConst(I)) + if (isTfrConst(*I)) continue; Defs.clear(); HBS::getInstrDefs(*I, Defs); |