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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-08-02 21:49:20 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-08-02 21:49:20 +0000 |
| commit | 824d347d2d3ffd04244bb5718f109436c231a20e (patch) | |
| tree | fbb53fa3d1fa9e185afa1b1f631ccee19088976f /llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | |
| parent | ca0d48b74299d218a3000825bb44fd40ca2017f6 (diff) | |
| download | llvm-824d347d2d3ffd04244bb5718f109436c231a20e.zip llvm-824d347d2d3ffd04244bb5718f109436c231a20e.tar.gz llvm-824d347d2d3ffd04244bb5718f109436c231a20e.tar.bz2 | |
[Hexagon] Recognize vcombine in copy propagation
llvm-svn: 277528
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index d8babdd..5db69ae 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1568,7 +1568,9 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B, continue; } - if (FRC == &Hexagon::DoubleRegsRegClass) { + if (FRC == &Hexagon::DoubleRegsRegClass || + FRC == &Hexagon::VecDblRegsRegClass || + FRC == &Hexagon::VecDblRegs128BRegClass) { // Try to generate REG_SEQUENCE. BitTracker::RegisterRef TL = { R, Hexagon::subreg_loreg }; BitTracker::RegisterRef TH = { R, Hexagon::subreg_hireg }; @@ -1602,6 +1604,8 @@ bool CopyPropagation::isCopyReg(unsigned Opc) { case Hexagon::A2_combinew: case Hexagon::A4_combineir: case Hexagon::A4_combineri: + case Hexagon::V6_vcombine: + case Hexagon::V6_vcombine_128B: return true; default: break; @@ -1639,7 +1643,9 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) { } break; } - case Hexagon::A2_combinew: { + case Hexagon::A2_combinew: + case Hexagon::V6_vcombine: + case Hexagon::V6_vcombine_128B: { BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); Changed = HBS::replaceSubWithSub(RD.Reg, Hexagon::subreg_loreg, RL.Reg, RL.Sub, MRI); |