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| author | Luke Lau <luke@igalia.com> | 2024-11-07 12:35:59 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-07 12:35:59 +0800 |
| commit | f0e2301b7c3f2576a4fbc53441e9378b966e21ef (patch) | |
| tree | de4c1b39bd433eb146a61f4d7a681bc96e2e31e3 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 481ff22b8b81bb5e2d40101b36eca3e90a7d1a5d (diff) | |
| download | llvm-f0e2301b7c3f2576a4fbc53441e9378b966e21ef.zip llvm-f0e2301b7c3f2576a4fbc53441e9378b966e21ef.tar.gz llvm-f0e2301b7c3f2576a4fbc53441e9378b966e21ef.tar.bz2 | |
[RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as legal interleaved access (#115257)
This is another piece split off from the work to add zvfhmin/zvfbfmin to
isLegalElementTypeForRVV.
This is needed to get InterleavedAccessPass to lower [de]interleaves to
segment load/stores.
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions