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| author | Hari Limaye <hari.limaye@arm.com> | 2025-09-08 14:14:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-08 14:14:24 +0100 |
| commit | e38392b19b3989222b1d2b248069f3fb36bfea7a (patch) | |
| tree | 42a074a79d18acc974f72f39bd7a3579c5c8b065 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 414f02855695f9b8006e55e932dc208a1f6656c1 (diff) | |
| download | llvm-e38392b19b3989222b1d2b248069f3fb36bfea7a.zip llvm-e38392b19b3989222b1d2b248069f3fb36bfea7a.tar.gz llvm-e38392b19b3989222b1d2b248069f3fb36bfea7a.tar.bz2 | |
[AArch64] Transform add(x, abs(y)) -> saba(x, y, 0) (#156615)
Add a DAGCombine to perform the following transformations:
- add(x, abs(y)) -> saba(x, y, 0)
- add(x, zext(abs(y))) -> sabal(x, y, 0)
As well as being a useful generic transformation, this also fixes an
issue where LLVM de-optimises [US]ABA neon ACLE intrinsics into separate
ABD+ADD instructions when one of the operands is a zero vector.
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions