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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2020-02-17 14:49:58 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2020-02-17 14:54:17 +0000 |
| commit | dad5f00e3b4d437fc1247d2d84efee924ae13201 (patch) | |
| tree | 5990a7b76104e2f0ba797447fc9dff9e6dbc3a50 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | f4c59c0f97cd64668c50547f23249017689717af (diff) | |
| download | llvm-dad5f00e3b4d437fc1247d2d84efee924ae13201.zip llvm-dad5f00e3b4d437fc1247d2d84efee924ae13201.tar.gz llvm-dad5f00e3b4d437fc1247d2d84efee924ae13201.tar.bz2 | |
[DAGCombine] Combine pattern for REV16
This adds another pattern to the combiner for a case that we were not handling
to generate the REV16 instruction for ARM/Thumb2 and a bswap+ror on X86.
Differential Revision: https://reviews.llvm.org/D74032
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions