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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-07-13 10:51:10 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-13 10:51:10 +0900 |
| commit | d92e6f0e81a4699c205d5cf023d9daeac1118cc5 (patch) | |
| tree | f3260808ba49c0267a08db37ccd25fbd005e832d /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 77bcde657b6107ed8f0918ea5aea9005b08817ab (diff) | |
| download | llvm-d92e6f0e81a4699c205d5cf023d9daeac1118cc5.zip llvm-d92e6f0e81a4699c205d5cf023d9daeac1118cc5.tar.gz llvm-d92e6f0e81a4699c205d5cf023d9daeac1118cc5.tar.bz2 | |
RISCV: Start moving runtime libcall config to tablegen (#147652)
This doesn't yet attempt to move the OS dependent configuration
shared with other targets. Removes __riscv_flush_icache from the
default set so it's no longer falsely reported as available for
other targets.
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions