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authorBenjamin Kramer <benny.kra@googlemail.com>2013-05-19 22:01:57 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2013-05-19 22:01:57 +0000
commit8bad66e586103a2ca59c98f423f270dbfec131e0 (patch)
tree852ecfd84a1fcb7e10c4c3880c500d9e9246e4b4 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parent86c5469d2675da06ee340f2f55d014ad1c652e16 (diff)
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Replace some bit operations with simpler ones. No functionality change.
llvm-svn: 182226
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d289637..c562cf7 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1224,7 +1224,7 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
}
// Empty register lists are not allowed.
- if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
+ if (Val == 0) return MCDisassembler::Fail;
for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))