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| author | Igor Breger <igor.breger@intel.com> | 2016-01-25 10:17:11 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2016-01-25 10:17:11 +0000 |
| commit | 6d421419db33a98c52a05a2aefd74492473d0512 (patch) | |
| tree | b50bc5f7f492b410e42b20659e75768ec53f0047 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | d3e1dede4a28dfffedc8b49177c2abb79a0649e7 (diff) | |
| download | llvm-6d421419db33a98c52a05a2aefd74492473d0512.zip llvm-6d421419db33a98c52a05a2aefd74492473d0512.tar.gz llvm-6d421419db33a98c52a05a2aefd74492473d0512.tar.bz2 | |
AVX1 : Enable vector masked_load/store to AVX1.
Use AVX1 FP instructions (vmaskmovps/pd) in place of the AVX2 int instructions (vpmaskmovd/q).
Differential Revision: http://reviews.llvm.org/D16528
llvm-svn: 258675
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions