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| author | David Greene <greened@obbligato.org> | 2019-05-28 15:37:01 +0000 |
|---|---|---|
| committer | David Greene <greened@obbligato.org> | 2019-05-28 15:37:01 +0000 |
| commit | 561fcc0d63caca46e46a746db482a1c6895b2ac4 (patch) | |
| tree | 03e64e5f43c058f13f56c24e964e43d39e29984e /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | ebe22a1774ed433534a63af0bf5fdc5b5bd821b4 (diff) | |
| download | llvm-561fcc0d63caca46e46a746db482a1c6895b2ac4.zip llvm-561fcc0d63caca46e46a746db482a1c6895b2ac4.tar.gz llvm-561fcc0d63caca46e46a746db482a1c6895b2ac4.tar.bz2 | |
[X86-64] Fix 256-bit SET0 lowering for non-VLX targets
If we don't have VLX then 256-bit SET0 should be lowered
to VPXOR with ZMM registers. This restores functionality
accidentally removed by r309926.
Differential Revision: https://reviews.llvm.org/D62415
llvm-svn: 361843
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions