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| author | Geoff Berry <gberry@codeaurora.org> | 2015-11-20 22:34:39 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2015-11-20 22:34:39 +0000 |
| commit | 5256fcada0ae3021b30bd1edc064beeffd0e41fc (patch) | |
| tree | 377fe6c37e5f791b40718c3171e6dd2addaad694 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 8638714dc72976c5d4f5afa6eaeccad2a06dce7f (diff) | |
| download | llvm-5256fcada0ae3021b30bd1edc064beeffd0e41fc.zip llvm-5256fcada0ae3021b30bd1edc064beeffd0e41fc.tar.gz llvm-5256fcada0ae3021b30bd1edc064beeffd0e41fc.tar.bz2 | |
[CodeGenPrepare] Create more extloads and fewer ands
Summary:
Add and instructions immediately after loads that only have their low
bits used, assuming that the (and (load x) c) will be matched as a
extload and the ands/truncs fed by the extload will be removed by isel.
Reviewers: mcrosier, qcolombet, ab
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D14584
llvm-svn: 253722
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions