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| author | Luke Lau <luke@igalia.com> | 2024-11-07 14:40:15 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-07 14:40:15 +0800 |
| commit | 343a810725f27bfe92fbd04a42d42aa9caaee7a6 (patch) | |
| tree | 742b2b52bb9ed001a80c09565ee7110c3a7d0a2b /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 9b058bb42d49afb61b07a7eeeea1ad3d1407f1c9 (diff) | |
| download | llvm-343a810725f27bfe92fbd04a42d42aa9caaee7a6.zip llvm-343a810725f27bfe92fbd04a42d42aa9caaee7a6.tar.gz llvm-343a810725f27bfe92fbd04a42d42aa9caaee7a6.tar.bz2 | |
[RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as legal strided access (#115264)
This is also split off from the zvfhmin/zvfbfmin
isLegalElementTypeForRVV work.
Enabling this will cause SLP and RISCVGatherScatterLowering to emit
@llvm.experimental.vp.strided.{load,store} intrinsics, and codegen
support for this was added in #109387 and #114750.
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions