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| author | Fangrui Song <i@maskray.me> | 2023-09-01 18:25:16 -0700 |
|---|---|---|
| committer | Fangrui Song <i@maskray.me> | 2023-09-01 18:25:16 -0700 |
| commit | 111fcb0df02db3db8bed1d5db6d911b7ce544d92 (patch) | |
| tree | be1a4370f8a99e3dc03cade7c29337b8c432686b /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 9f3e3efd98a29eb8df9e3ad43a573c9141d1ace2 (diff) | |
| download | llvm-111fcb0df02db3db8bed1d5db6d911b7ce544d92.zip llvm-111fcb0df02db3db8bed1d5db6d911b7ce544d92.tar.gz llvm-111fcb0df02db3db8bed1d5db6d911b7ce544d92.tar.bz2 | |
[llvm] Fix duplicate word typos. NFC
Those fixes were taken from https://reviews.llvm.org/D137338
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index ee81bfa..def54f9 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -6204,7 +6204,7 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, // We have to check if the instruction is MRRC2 // or MCRR2 when constructing the operands for // Inst. Reason is because MRRC2 stores to two - // registers so it's tablegen desc has has two + // registers so it's tablegen desc has two // outputs whereas MCRR doesn't store to any // registers so all of it's operands are listed // as inputs, therefore the operand order for |