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| author | Eugene Zelenko <eugene.zelenko@gmail.com> | 2017-09-20 21:35:51 +0000 |
|---|---|---|
| committer | Eugene Zelenko <eugene.zelenko@gmail.com> | 2017-09-20 21:35:51 +0000 |
| commit | 076468c0d029c237a36972b8877908b549dae416 (patch) | |
| tree | a3d41b2e0ac2e83ee1d46c80489a8027b0395559 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 562630a1feb92e3f6854056364b18e29eefa0ecd (diff) | |
| download | llvm-076468c0d029c237a36972b8877908b549dae416.zip llvm-076468c0d029c237a36972b8877908b549dae416.tar.gz llvm-076468c0d029c237a36972b8877908b549dae416.tar.bz2 | |
[ARM] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 313823
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 472df5b..e8bfa6b 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1,4 +1,4 @@ -//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// +//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// // // The LLVM Compiler Infrastructure // @@ -10,6 +10,7 @@ #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMBaseInfo.h" #include "MCTargetDesc/ARMMCTargetDesc.h" +#include "Utils/ARMBaseInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" @@ -31,7 +32,7 @@ using namespace llvm; #define DEBUG_TYPE "arm-disassembler" -typedef MCDisassembler::DecodeStatus DecodeStatus; +using DecodeStatus = MCDisassembler::DecodeStatus; namespace { @@ -117,6 +118,7 @@ public: private: mutable ITStatus ITBlock; + DecodeStatus AddThumbPredicate(MCInst&) const; void UpdateThumbVFPPredicate(MCInst&) const; }; @@ -2759,7 +2761,6 @@ static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, break; } - // First input register switch (Inst.getOpcode()) { case ARM::VST1q16: @@ -3858,7 +3859,6 @@ static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, return S; } - static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { unsigned imm = fieldFromInstruction(Insn, 0, 7); @@ -4182,7 +4182,6 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - unsigned R = fieldFromInstruction(Val, 5, 1); unsigned SysM = fieldFromInstruction(Val, 0, 5); |