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author | Tomas Matheson <tomas.matheson@arm.com> | 2024-02-29 09:48:29 +0000 |
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committer | Tomas Matheson <tomas.matheson@arm.com> | 2024-02-29 09:48:29 +0000 |
commit | 03420f570e92ee96133baa8feabc43148e322963 (patch) | |
tree | 2a7291745bb155d934daf0ef25eb17ef972199fb /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
parent | de5518836e16be3fbfce78394adc96d9bf70f2a5 (diff) | |
download | llvm-03420f570e92ee96133baa8feabc43148e322963.zip llvm-03420f570e92ee96133baa8feabc43148e322963.tar.gz llvm-03420f570e92ee96133baa8feabc43148e322963.tar.bz2 |
Revert "[llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116)"
This reverts commit 634b0243b8f7acc85af4f16b70e91d86ded4dc83.
Failing EXPENSIVE_CHECKS builds with "undefined physical register".
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 705f3cbc..604f22d 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -700,9 +700,6 @@ DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder); -static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, - uint64_t Address, - const MCDisassembler *Decoder); #include "ARMGenDisassemblerTables.inc" @@ -7033,23 +7030,3 @@ static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, return DS; } - -static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, - uint64_t Address, - const MCDisassembler *Decoder) { - DecodeStatus S = MCDisassembler::Success; - - const unsigned Rn = fieldFromInstruction(Insn, 16, 4); - // Adding Rn, holding memory location to save/load to/from, the only argument - // that is being encoded. - // '$Rn' in the assembly. - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler::Fail; - // An optional predicate, '$p' in the assembly. - DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder); - // An immediate that represents a floating point registers list. '$regs' in - // the assembly. - Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect. - - return S; -} |