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author | Reid Kleckner <rnk@google.com> | 2016-01-15 18:31:29 +0000 |
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committer | Reid Kleckner <rnk@google.com> | 2016-01-15 18:31:29 +0000 |
commit | 47f2452da84f820addf92cb003e7d4905d4aa1bc (patch) | |
tree | 99e240e8c16e486417128e744d8ea633c3588e14 /llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
parent | 79db917139bb0314b5e53a18996d84c57eeeb2fb (diff) | |
download | llvm-47f2452da84f820addf92cb003e7d4905d4aa1bc.zip llvm-47f2452da84f820addf92cb003e7d4905d4aa1bc.tar.gz llvm-47f2452da84f820addf92cb003e7d4905d4aa1bc.tar.bz2 |
# This is a combination of 2 commits.
# The first commit's message is:
Revert "[ARM] Add DSP build attribute and extension targeting"
This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc.
# This is the 2nd commit message:
Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline"
This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5.
llvm-svn: 257916
Diffstat (limited to 'llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index fb72b20..277304d 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -272,12 +272,6 @@ class ARMAsmParser : public MCTargetAsmParser { bool hasV8MBaseline() const { return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps]; } - bool hasV8MMainline() const { - return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps]; - } - bool has8MSecExt() const { - return getSTI().getFeatureBits()[ARM::Feature8MSecExt]; - } bool hasARM() const { return !getSTI().getFeatureBits()[ARM::FeatureNoARM]; } @@ -3978,18 +3972,6 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { .Case("basepri_max", 0x812) .Case("faultmask", 0x813) .Case("control", 0x814) - .Case("msplim", 0x80a) - .Case("psplim", 0x80b) - .Case("msp_ns", 0x888) - .Case("psp_ns", 0x889) - .Case("msplim_ns", 0x88a) - .Case("psplim_ns", 0x88b) - .Case("primask_ns", 0x890) - .Case("basepri_ns", 0x891) - .Case("basepri_max_ns", 0x892) - .Case("faultmask_ns", 0x893) - .Case("control_ns", 0x894) - .Case("sp_ns", 0x898) .Default(~0U); if (FlagsVal == ~0U) @@ -4004,14 +3986,6 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { // basepri, basepri_max and faultmask only valid for V7m. return MatchOperand_NoMatch; - if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b || - (FlagsVal > 0x814 && FlagsVal < 0xc00))) - return MatchOperand_NoMatch; - - if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b || - (FlagsVal > 0x890 && FlagsVal <= 0x893))) - return MatchOperand_NoMatch; - Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); return MatchOperand_Success; |