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author | Tim Northover <tnorthover@apple.com> | 2015-10-28 22:46:43 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2015-10-28 22:46:43 +0000 |
commit | e0ccdc6de93e879723c3b1af658913cbc0b8fbdc (patch) | |
tree | 7caa8763e15e0633a44465e9bb7658d9ff1d1f97 /llvm/lib/Target/ARM/ARMSubtarget.cpp | |
parent | 2d4d1615197efeb044f62d6a8721704839cd5337 (diff) | |
download | llvm-e0ccdc6de93e879723c3b1af658913cbc0b8fbdc.zip llvm-e0ccdc6de93e879723c3b1af658913cbc0b8fbdc.tar.gz llvm-e0ccdc6de93e879723c3b1af658913cbc0b8fbdc.tar.bz2 |
ARM: add backend support for the ABI used in WatchOS
At the LLVM level this ABI is essentially a minimal modification of AAPCS to
support 16-byte alignment for vector types and the stack.
llvm-svn: 251570
Diffstat (limited to 'llvm/lib/Target/ARM/ARMSubtarget.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index e0d9939..aea452c 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -155,11 +155,18 @@ void ARMSubtarget::initializeEnvironment() { void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { if (CPUString.empty()) { - if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s")) - // Default to the Swift CPU when targeting armv7s/thumbv7s. - CPUString = "swift"; - else - CPUString = "generic"; + CPUString = "generic"; + + if (isTargetDarwin()) { + StringRef ArchName = TargetTriple.getArchName(); + if (ArchName.endswith("v7s")) + // Default to the Swift CPU when targeting armv7s/thumbv7s. + CPUString = "swift"; + else if (ArchName.endswith("v7k")) + // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k. + // ARMv7k does not use SjLj exception handling. + CPUString = "cortex-a7"; + } } // Insert the architecture feature derived from the target triple into the @@ -190,7 +197,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { if (isAAPCS_ABI()) stackAlignment = 8; - if (isTargetNaCl()) + if (isTargetNaCl() || isAAPCS16_ABI()) stackAlignment = 16; // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo:: @@ -241,8 +248,14 @@ bool ARMSubtarget::isAPCS_ABI() const { } bool ARMSubtarget::isAAPCS_ABI() const { assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN); - return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS; + return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS || + TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16; } +bool ARMSubtarget::isAAPCS16_ABI() const { + assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN); + return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16; +} + /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. bool |