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| author | Chris Lattner <sabre@nondot.org> | 2008-01-06 08:36:04 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-01-06 08:36:04 +0000 |
| commit | 10324d01754c2848ccfb5b30149bedada6767591 (patch) | |
| tree | 2a016724aa9efd853a5de6a96f1aef42de28f39d /llvm/lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | 1694a53c5d632c1859f3f32f8603cafb365c0c4e (diff) | |
| download | llvm-10324d01754c2848ccfb5b30149bedada6767591.zip llvm-10324d01754c2848ccfb5b30149bedada6767591.tar.gz llvm-10324d01754c2848ccfb5b30149bedada6767591.tar.bz2 | |
rename isStore -> mayStore to more accurately reflect what it captures.
llvm-svn: 45656
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp index b940052..ea775f7 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp @@ -905,7 +905,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); else // tLDR has an extra register operand. MI.addOperand(MachineOperand::CreateReg(0, false)); - } else if (TII.isStore(Opcode)) { + } else if (TII.mayStore(Opcode)) { // FIXME! This is horrific!!! We need register scavenging. // Our temporary workaround has marked r3 unavailable. Of course, r3 is // also a ABI register so it's possible that is is the register that is |