aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff options
context:
space:
mode:
authorDan Gohman <gohman@apple.com>2008-10-03 15:45:36 +0000
committerDan Gohman <gohman@apple.com>2008-10-03 15:45:36 +0000
commit0d1e9a8e0401048b5619dd46afb744af7b028aff (patch)
tree0b150971be1244ee265f214d4bcad572ace4128f /llvm/lib/Target/ARM/ARMRegisterInfo.cpp
parent6d8e67f512cabbd7745d4dd71b710806a8abc166 (diff)
downloadllvm-0d1e9a8e0401048b5619dd46afb744af7b028aff.zip
llvm-0d1e9a8e0401048b5619dd46afb744af7b028aff.tar.gz
llvm-0d1e9a8e0401048b5619dd46afb744af7b028aff.tar.bz2
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc. llvm-svn: 57006
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterInfo.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index 3a0a57d..2091899 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -540,7 +540,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
bool isThumb = AFI->isThumbFunction();
- while (!MI.getOperand(i).isFrameIndex()) {
+ while (!MI.getOperand(i).isFI()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
@@ -1020,7 +1020,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
- if (I->getOperand(i).isFrameIndex()) {
+ if (I->getOperand(i).isFI()) {
unsigned Opcode = I->getOpcode();
const TargetInstrDesc &Desc = TII.get(Opcode);
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
@@ -1086,7 +1086,7 @@ static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
int Opc, unsigned Area,
const ARMSubtarget &STI) {
while (MBBI != MBB.end() &&
- MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
+ MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
if (Area != 0) {
bool Done = false;
unsigned Category = 0;
@@ -1250,7 +1250,7 @@ static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
return ((MI->getOpcode() == ARM::FLDD ||
MI->getOpcode() == ARM::LDR ||
MI->getOpcode() == ARM::tRestore) &&
- MI->getOperand(1).isFrameIndex() &&
+ MI->getOperand(1).isFI() &&
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
}