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| author | Hsiangkai Wang <kai.wang@sifive.com> | 2021-02-18 14:52:19 +0800 |
|---|---|---|
| committer | Hsiangkai Wang <kai.wang@sifive.com> | 2021-02-18 22:17:00 +0800 |
| commit | f1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece (patch) | |
| tree | e019b495ff309e111457d73ad3be1bfc2f4423d8 /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | b97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2 (diff) | |
| download | llvm-f1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece.zip llvm-f1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece.tar.gz llvm-f1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece.tar.bz2 | |
[RISCV] Fix bugs in pseudo instructions for masked segment load.
For masked segment load, the destination register should not overlap
with mask register. It could not be V0.
In the original implementation, there is no segment load/store register
class without V0. In this patch, I added these register classes and
modify `GetVRegNoV0` to get the correct one.
Differential Revision: https://reviews.llvm.org/D96937
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
0 files changed, 0 insertions, 0 deletions