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author | Krzysztof Drewniak <Krzysztof.Drewniak@amd.com> | 2023-04-17 21:49:02 +0000 |
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committer | Krzysztof Drewniak <Krzysztof.Drewniak@amd.com> | 2023-05-03 21:18:48 +0000 |
commit | cc4703745ffa398b66f985b483cb8b61eb2ed425 (patch) | |
tree | 6c9a6e7cfcf89e9b306269c95a9dce1e29b6c659 /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
parent | 98c1104d41efae7cee6b0f2c833367c1c7231c4c (diff) | |
download | llvm-cc4703745ffa398b66f985b483cb8b61eb2ed425.zip llvm-cc4703745ffa398b66f985b483cb8b61eb2ed425.tar.gz llvm-cc4703745ffa398b66f985b483cb8b61eb2ed425.tar.bz2 |
[mlir][AMDGPU] Add emulation pass for atomics on AMDGPU targets
Not all AMDGPU targets support all atomic operations. For example,
there are not atomic floating-point adds on the gfx10 series. Add a
pass to emulate these operations using a compare-and-swap loop, by
analogy to the generic atomicrmw rewrite in MemrefToLLVM.
This pass is named generally, as in the future we may have a
memref-to-amdgpu that translates constructs like atomicrmw fmax (which
doesn't generally exist in LLVM) to the relevant intrinsics, which may
themselves require emulation.
Since the AMDGPU dialect now has a pass that operates on it, the
dialect's directory structure is reorganized to match other similarly
complex dialects.
The pass should be run before amdgpu-to-rocdl if desired.
This commit also adds f64 support to atomic_fmax.
Depends on D148722
Reviewed By: nirvedhmeshram
Differential Revision: https://reviews.llvm.org/D148724
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
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