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| author | Chad Rosier <mcrosier@apple.com> | 2013-03-25 16:29:20 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2013-03-25 16:29:20 +0000 |
| commit | ace9c5dfaf09430f10e677e3646eb8df9e9fe9a6 (patch) | |
| tree | cb0ba8e61e249fb5ce54749eed4a10c260257eea /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 82050340c6b74e91d6e1b62006f9645d1dc4bc74 (diff) | |
| download | llvm-ace9c5dfaf09430f10e677e3646eb8df9e9fe9a6.zip llvm-ace9c5dfaf09430f10e677e3646eb8df9e9fe9a6.tar.gz llvm-ace9c5dfaf09430f10e677e3646eb8df9e9fe9a6.tar.bz2 | |
[arm load/store optimizer] When trying to merge a base update load/store, make
sure the base register and would-be writeback register don't conflict for
stores. This was already being done for loads.
Unfortunately, it is rather difficult to create a test case for this issue. It
was exposed in 450.soplex at LTO and requires unlucky register allocation.
<rdar://13394908>
llvm-svn: 177874
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 98bd6c1..e4e683c 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -865,7 +865,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB, bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD; // Can't do the merge if the destination register is the same as the would-be // writeback register. - if (isLd && MI->getOperand(0).getReg() == Base) + if (MI->getOperand(0).getReg() == Base) return false; unsigned PredReg = 0; |