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| author | Tony Tye <Tony.Tye@amd.com> | 2021-07-23 19:38:36 +0000 |
|---|---|---|
| committer | Tony Tye <Tony.Tye@amd.com> | 2021-08-10 08:43:03 +0000 |
| commit | 53eb469195b89a00c5e977fc7f76cd520a447d97 (patch) | |
| tree | 3d63fd5c0a0dde645fcd1d6eba5ead222ca6cc92 /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 6794593fdbf5209bf6f376ce975820bcf5526e83 (diff) | |
| download | llvm-53eb469195b89a00c5e977fc7f76cd520a447d97.zip llvm-53eb469195b89a00c5e977fc7f76cd520a447d97.tar.gz llvm-53eb469195b89a00c5e977fc7f76cd520a447d97.tar.bz2 | |
[AMDGPU] Support non-strictly stronger memory orderings in SIMemoryLegalizer
C++20 no longer requires the failure memory ordering to be no stronger than the
success memory ordering. Adjust assert in AMD GPU SIMemoryLegalizer, and merge
instruction memory orderings
Add common operation to merge memory orders that allows non strict memory
orderings to be combined. Use it in SIMemoryLegalizer and
MachineMemOperand::getMergedOrdering.
Reviewed By: efriedma, rampitec
Differential Revision: https://reviews.llvm.org/D106729
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
0 files changed, 0 insertions, 0 deletions