- More refactoring. This gets rid of all of the getOpcode calls.

- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300

1 files changed, 0 insertions, 13 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index e186729..c9d5ac1 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -62,19 +62,6 @@ getUnindexedOpcode(unsigned Opc) const {
   return 0;
 }
 
-unsigned ARMInstrInfo::
-getOpcode(ARMII::Op Op) const {
-  switch (Op) {
-  case ARMII::ADDri: return ARM::ADDri;
-  case ARMII::MOVr: return ARM::MOVr;
-  case ARMII::SUBri: return ARM::SUBri;
-  default:
-    break;
-  }
-
-  return 0;
-}
-
 bool ARMInstrInfo::
 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
   if (MBB.empty()) return false;