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| author | Jie Fu <jiefu@tencent.com> | 2025-06-28 19:29:00 +0800 |
|---|---|---|
| committer | Jie Fu <jiefu@tencent.com> | 2025-06-28 19:29:00 +0800 |
| commit | feb61f5b0529a18ce819e9be91d8510bbdd737f7 (patch) | |
| tree | 6c491b47edc51eeed9077bfc20815ee614e66bef /llvm/lib/Target/ARM/ARMFrameLowering.cpp | |
| parent | 5ea29f77b9f809a3a33de72033e21225ec292170 (diff) | |
| download | llvm-feb61f5b0529a18ce819e9be91d8510bbdd737f7.zip llvm-feb61f5b0529a18ce819e9be91d8510bbdd737f7.tar.gz llvm-feb61f5b0529a18ce819e9be91d8510bbdd737f7.tar.bz2 | |
[Target] Prevent copying in loop variables (NFC)
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2769:19: error: loop variable '[Reg, N]' creates a copy from type 'std::pair<unsigned int, llvm::SDValue> const' [-Werror,-Wrange-loop-construct]
for (const auto [Reg, N] : RegsToPass) {
^
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2769:8: note: use reference type 'std::pair<unsigned int, llvm::SDValue> const &' to prevent copying
for (const auto [Reg, N] : RegsToPass) {
^~~~~~~~~~~~~~~~~~~~~
&
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2954:19: error: loop variable '[Reg, N]' creates a copy from type 'std::pair<unsigned int, llvm::SDValue> const' [-Werror,-Wrange-loop-construct]
for (const auto [Reg, N] : RegsToPass)
^
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2954:8: note: use reference type 'std::pair<unsigned int, llvm::SDValue> const &' to prevent copying
for (const auto [Reg, N] : RegsToPass)
^~~~~~~~~~~~~~~~~~~~~
&
2 errors generated.
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFrameLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 74a75a8..50d8eee 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1701,7 +1701,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, .addReg(ARM::SP) .setMIFlags(MachineInstr::FrameSetup) .add(predOps(ARMCC::AL)); - for (const auto [Reg, Kill] : Regs) + for (const auto &[Reg, Kill] : Regs) MIB.addReg(Reg, getKillRegState(Kill)); } else if (Regs.size() == 1) { BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) |