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| author | Weiming Zhao <weimingz@codeaurora.org> | 2016-05-04 18:19:33 +0000 |
|---|---|---|
| committer | Weiming Zhao <weimingz@codeaurora.org> | 2016-05-04 18:19:33 +0000 |
| commit | 2373f769cefbd4213d46fb6df01bf453e7981ea9 (patch) | |
| tree | 4189691dc45cd12205956189b90f489d544e4f4c /llvm/lib/Target/ARM/ARMFrameLowering.cpp | |
| parent | dea877ca496168eec06493cfdd4fcd2059613b64 (diff) | |
| download | llvm-2373f769cefbd4213d46fb6df01bf453e7981ea9.zip llvm-2373f769cefbd4213d46fb6df01bf453e7981ea9.tar.gz llvm-2373f769cefbd4213d46fb6df01bf453e7981ea9.tar.bz2 | |
[ARM] Fix Scavenger assert due to underestimated stack size
Summary:
Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure.
Reviewers: rengolin
Subscribers: aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits
Differential Revision: http://reviews.llvm.org/D19896
llvm-svn: 268529
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFrameLowering.cpp | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 808a21f..cc026d8 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1479,6 +1479,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, bool CS1Spilled = false; bool LRSpilled = false; unsigned NumGPRSpills = 0; + unsigned NumFPRSpills = 0; SmallVector<unsigned, 4> UnspilledCS1GPRs; SmallVector<unsigned, 4> UnspilledCS2GPRs; const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( @@ -1533,8 +1534,17 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, CanEliminateFrame = false; } - if (!ARM::GPRRegClass.contains(Reg)) + if (!ARM::GPRRegClass.contains(Reg)) { + if (Spilled) { + if (ARM::SPRRegClass.contains(Reg)) + NumFPRSpills++; + else if (ARM::DPRRegClass.contains(Reg)) + NumFPRSpills += 2; + else if (ARM::QPRRegClass.contains(Reg)) + NumFPRSpills += 4; + } continue; + } if (Spilled) { NumGPRSpills++; @@ -1607,11 +1617,14 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, // FIXME: We could add logic to be more precise about negative offsets // and which instructions will need a scratch register for them. Is it // worth the effort and added fragility? - bool BigStack = (RS && (MFI->estimateStackSize(MF) + - ((hasFP(MF) && AFI->hasStackFrame()) ? 4 : 0) >= - estimateRSStackSizeLimit(MF, this))) || - MFI->hasVarSizedObjects() || - (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); + auto ArgStackSize = MF.getInfo<ARMFunctionInfo>()->getArgumentStackSize(); + bool BigStack = + (RS && (MFI->estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills) + + (!hasFP(MF) ? ArgStackSize : 0) + 16 /* possible paddings */ + + ((hasFP(MF) && AFI->hasStackFrame()) ? 4 : 0) >= + estimateRSStackSizeLimit(MF, this))) || + MFI->hasVarSizedObjects() || + (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); bool ExtraCSSpill = false; if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { |