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| author | David Blaikie <dblaikie@gmail.com> | 2015-01-29 20:23:47 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-01-29 20:23:47 +0000 |
| commit | 67545305aab865114ac8fa025cd7c1cc88fcc840 (patch) | |
| tree | 2dbf5d3ddf422d348de525c5e1e4b124c3f1532c /llvm/lib/Target/ARM/ARMFastISel.cpp | |
| parent | 24adfbc20c238aa1198a2849a897c4fd6b13aa90 (diff) | |
| download | llvm-67545305aab865114ac8fa025cd7c1cc88fcc840.zip llvm-67545305aab865114ac8fa025cd7c1cc88fcc840.tar.gz llvm-67545305aab865114ac8fa025cd7c1cc88fcc840.tar.bz2 | |
Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps.
llvm-svn: 227488
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 375d394..3d4c200 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -169,7 +169,7 @@ class ARMFastISel final : public FastISel { bool isTypeLegal(Type *Ty, MVT &VT); bool isLoadTypeLegal(Type *Ty, MVT &VT); bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, - bool isZExt); + bool isZExt, DebugLoc CurDL); bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment = 0, bool isZExt = true, bool allocReg = true); @@ -1273,7 +1273,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { if (ARMPred == ARMCC::AL) return false; // Emit the compare. - if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) + if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(), CI->getDebugLoc())) return false; unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; @@ -1363,7 +1363,7 @@ bool ARMFastISel::SelectIndirectBr(const Instruction *I) { } bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, - bool isZExt) { + bool isZExt, DebugLoc CurDL) { Type *Ty = Src1Value->getType(); EVT SrcEVT = TLI.getValueType(Ty, true); if (!SrcEVT.isSimple()) return false; @@ -1458,11 +1458,11 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); if (!UseImm) { SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDL, II) .addReg(SrcReg1).addReg(SrcReg2)); } else { MachineInstrBuilder MIB; - MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDL, II) .addReg(SrcReg1); // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0. @@ -1474,7 +1474,7 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, // For floating point we need to move the result to a comparison register // that we can then use for branches. if (Ty->isFloatTy() || Ty->isDoubleTy()) - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDL, TII.get(ARM::FMSTAT))); return true; } @@ -1489,7 +1489,7 @@ bool ARMFastISel::SelectCmp(const Instruction *I) { if (ARMPred == ARMCC::AL) return false; // Emit the compare. - if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) + if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(), CI->getDebugLoc())) return false; // Now set a register based on the comparison. Explicitly set the predicates |