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author | dyung <douglas.yung@sony.com> | 2024-11-07 10:02:51 -0800 |
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committer | GitHub <noreply@github.com> | 2024-11-07 13:02:51 -0500 |
commit | bc7e099aa82d44b5682ec3dbd1322ccc5000a50d (patch) | |
tree | 07c38b013adf0f7e798a674b0ac31475acd7e71b /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | |
parent | 5f4e3a3ced525c84a5268e51a56fe47b5456fd81 (diff) | |
download | llvm-bc7e099aa82d44b5682ec3dbd1322ccc5000a50d.zip llvm-bc7e099aa82d44b5682ec3dbd1322ccc5000a50d.tar.gz llvm-bc7e099aa82d44b5682ec3dbd1322ccc5000a50d.tar.bz2 |
Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes" (#115353)
Reverts llvm/llvm-project#115291
Reverting due to test failures on many bots including
https://lab.llvm.org/buildbot/#/builders/174/builds/8049
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 2ddcd5a..1e43d27 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -694,22 +694,22 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo( const llvm::MachineFunction &MF) : ExplicitKernArgSize(MFI.getExplicitKernArgSize()), MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()), - GDSSize(MFI.getGDSSize()), DynLDSAlign(MFI.getDynLDSAlign()), - IsEntryFunction(MFI.isEntryFunction()), + GDSSize(MFI.getGDSSize()), + DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()), NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()), MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()), HasSpilledSGPRs(MFI.hasSpilledSGPRs()), HasSpilledVGPRs(MFI.hasSpilledVGPRs()), HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()), Occupancy(MFI.getOccupancy()), - NumPhysicalVGPRSpillLanes(MFI.getNumPhysicalVGPRSpillLanes()), ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)), FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)), StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)), BytesInStackArgArea(MFI.getBytesInStackArgArea()), ReturnsVoid(MFI.returnsVoid()), ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), - PSInputAddr(MFI.getPSInputAddr()), PSInputEnable(MFI.getPSInputEnable()), + PSInputAddr(MFI.getPSInputAddr()), + PSInputEnable(MFI.getPSInputEnable()), Mode(MFI.getMode()) { for (Register Reg : MFI.getSGPRSpillPhysVGPRs()) SpillPhysVGPRS.push_back(regToString(Reg, TRI)); @@ -754,7 +754,6 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields( HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs; BytesInStackArgArea = YamlMFI.BytesInStackArgArea; ReturnsVoid = YamlMFI.ReturnsVoid; - NumPhysicalVGPRSpillLanes = YamlMFI.NumPhysicalVGPRSpillLanes; if (YamlMFI.ScavengeFI) { auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo()); |