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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-07-25 19:49:56 +0900 |
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committer | GitHub <noreply@github.com> | 2025-07-25 19:49:56 +0900 |
commit | 2b1ce25e21765a07f69c48196bd15239d98cae92 (patch) | |
tree | 80b7c3cab8b8625d2556c4a34db0aedf2634e11f /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | |
parent | 129a35454ccb1d535b6cdd5cc768ab0b2897f889 (diff) | |
download | llvm-2b1ce25e21765a07f69c48196bd15239d98cae92.zip llvm-2b1ce25e21765a07f69c48196bd15239d98cae92.tar.gz llvm-2b1ce25e21765a07f69c48196bd15239d98cae92.tar.bz2 |
AMDGPU: Fix -amdgpu-mfma-vgpr-form flag on gfx908 (#150599)
This should be ignored since there are no VGPR forms. This
makes it possible to flip the default for the flag to true.
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index f0be204..9a1448f 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -81,11 +81,15 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F, PSInputAddr = AMDGPU::getInitialPSInputAddr(F); } - MayNeedAGPRs = ST.hasMAIInsts() && !MFMAVGPRForm; - if (!MFMAVGPRForm && ST.hasGFX90AInsts() && - ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() && - !mayUseAGPRs(F)) - MayNeedAGPRs = false; // We will select all MAI with VGPR operands. + MayNeedAGPRs = ST.hasMAIInsts(); + if (ST.hasGFX90AInsts()) { + // FIXME: MayNeedAGPRs is a misnomer for how this is used. MFMA selection + // should be separated from availability of AGPRs + if (MFMAVGPRForm || + (ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() && + !mayUseAGPRs(F))) + MayNeedAGPRs = false; // We will select all MAI with VGPR operands. + } if (AMDGPU::isChainCC(CC)) { // Chain functions don't receive an SP from their caller, but are free to |