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authorMatt Arsenault <Matthew.Arsenault@amd.com>2021-11-23 19:47:40 -0500
committerMatt Arsenault <Matthew.Arsenault@amd.com>2022-02-02 19:05:05 -0500
commitd6fdbbcace0b51c0096c5dbab6afb6449da21524 (patch)
treef37236451f690227613a68503824b5e7cfac048e /llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
parent85628ce75b3084dc0f185a320152baf85b59aba7 (diff)
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AMDGPU: Add second emergency slot for SGPR to vmem for large frames
In a future change, we will sometimes use a VGPR offset for doing spills to memory, in which case we need 2 free VGPRs to do the SGPR spill. In most cases we could spill the VGPR along with the SGPR being spilled, but we don't have any free lanes for SGPR_1024 in wave32 so we could still potentially need a second scavenging slot.
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 0fbdbef..ddc1944 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -321,7 +321,7 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
// free frame index ids by the later pass(es) like "stack slot coloring"
// which in turn could mess-up with the book keeping of "frame index to VGPR
// lane".
- FuncInfo->removeDeadFrameIndices(MFI);
+ FuncInfo->removeDeadFrameIndices(MFI, /*ResetSGPRSpillStackIDs*/ false);
MadeChange = true;
}