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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-09-12 19:22:02 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-12 19:22:02 +0900 |
| commit | 7289f2cd0c371b2539faa628ec0eea58fa61892c (patch) | |
| tree | d5b7335a9d5f0f6dfceaf6791f4f0bcadca02142 /llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | |
| parent | 83b48b13f3a70bf56053e92593270c519859cfd7 (diff) | |
| download | llvm-7289f2cd0c371b2539faa628ec0eea58fa61892c.zip llvm-7289f2cd0c371b2539faa628ec0eea58fa61892c.tar.gz llvm-7289f2cd0c371b2539faa628ec0eea58fa61892c.tar.bz2 | |
CodeGen: Remove MachineFunction argument from getRegClass (#158188)
This is a low level utility to parse the MCInstrInfo and should
not depend on the state of the function.
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index 69d02e7..f0d1117 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -1337,10 +1337,10 @@ SILoadStoreOptimizer::checkAndPrepareMerge(CombineInfo &CI, AMDGPU::OpName::data1); const TargetRegisterClass *DataRC0 = - TII->getRegClass(Write2Opc, Data0Idx, TRI, *MF); + TII->getRegClass(Write2Opc, Data0Idx, TRI); const TargetRegisterClass *DataRC1 = - TII->getRegClass(Write2Opc, Data1Idx, TRI, *MF); + TII->getRegClass(Write2Opc, Data1Idx, TRI); if (unsigned SubReg = Data0->getSubReg()) { DataRC0 = TRI->getMatchingSuperRegClass(MRI->getRegClass(Data0->getReg()), |