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| author | Stanislav Mekhanoshin <rampitec@users.noreply.github.com> | 2024-02-19 13:45:23 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-19 13:45:23 -0800 |
| commit | 13e64958a00f9f47fc71027d5b6196906cbc2863 (patch) | |
| tree | b9ac07e9905506fabade408a0752b1ec326655f4 /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h | |
| parent | 35f45926eb12b2612f23012ab1e80e3be86dbb2d (diff) | |
| download | llvm-13e64958a00f9f47fc71027d5b6196906cbc2863.zip llvm-13e64958a00f9f47fc71027d5b6196906cbc2863.tar.gz llvm-13e64958a00f9f47fc71027d5b6196906cbc2863.tar.bz2 | |
[AMDGPU] Fix decoder for BF16 inline constants (#82276)
Fix #82039.
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index 02feaf55..3142b8a 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -15,6 +15,7 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H +#include "SIDefines.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/SmallString.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" @@ -231,25 +232,29 @@ public: unsigned getTtmpClassId(const OpWidthTy Width) const; static MCOperand decodeIntImmed(unsigned Imm); - static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm); + static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm, + AMDGPU::OperandSemantics Sema); MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const; MCOperand decodeLiteralConstant(bool ExtendFP64) const; - MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, - bool MandatoryLiteral = false, unsigned ImmWidth = 0, - bool IsFP = false) const; + MCOperand decodeSrcOp( + const OpWidthTy Width, unsigned Val, bool MandatoryLiteral = false, + unsigned ImmWidth = 0, + AMDGPU::OperandSemantics Sema = AMDGPU::OperandSemantics::INT) const; - MCOperand decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, - bool MandatoryLiteral = false, - unsigned ImmWidth = 0, bool IsFP = false) const; + MCOperand decodeNonVGPRSrcOp( + const OpWidthTy Width, unsigned Val, bool MandatoryLiteral = false, + unsigned ImmWidth = 0, + AMDGPU::OperandSemantics Sema = AMDGPU::OperandSemantics::INT) const; MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const; MCOperand decodeSpecialReg32(unsigned Val) const; MCOperand decodeSpecialReg64(unsigned Val) const; MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, - unsigned ImmWidth = 0) const; + unsigned ImmWidth, + AMDGPU::OperandSemantics Sema) const; MCOperand decodeSDWASrc16(unsigned Val) const; MCOperand decodeSDWASrc32(unsigned Val) const; MCOperand decodeSDWAVopcDst(unsigned Val) const; |