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| author | Joe Nash <Joseph.Nash@amd.com> | 2022-05-25 14:09:11 -0400 |
|---|---|---|
| committer | Joe Nash <Joseph.Nash@amd.com> | 2022-06-24 11:08:39 -0400 |
| commit | 07b7fada73da5e371607cf42b60b5d1a2706ad1c (patch) | |
| tree | 296e3336f92a1c166c4997099fee14463411ccf0 /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h | |
| parent | 78a31bb96961b30222f96d45b589bad7bc957cb4 (diff) | |
| download | llvm-07b7fada73da5e371607cf42b60b5d1a2706ad1c.zip llvm-07b7fada73da5e371607cf42b60b5d1a2706ad1c.tar.gz llvm-07b7fada73da5e371607cf42b60b5d1a2706ad1c.tar.bz2 | |
[AMDGPU] gfx11 VOPD instructions MC support
VOPD is a new encoding for dual-issue instructions for use in wave32.
This patch includes MC layer support only.
A VOPD instruction is constituted of an X component (for which there are
13 possible opcodes) and a Y component (for which there are the 13 X
opcodes plus 3 more). Most of the complexity in defining and parsing
a VOPD operation arises from the possible different total numbers of
operands and deferred parsing of certain operands depending on the
constituent X and Y opcodes.
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D128218
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index c6717ef..31869f0 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -233,6 +233,7 @@ public: MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral = false) const; MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const; + MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const; MCOperand decodeSpecialReg32(unsigned Val) const; MCOperand decodeSpecialReg64(unsigned Val) const; |