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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-27 15:46:01 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-27 15:46:01 +0000 |
| commit | f66bdb5ea8658fdcbac75f96a73e906f380e5741 (patch) | |
| tree | 2d5dcce4c69fb7cf858793c93b5d7a1dc115413a /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | |
| parent | 514f05543f2493450e8265a850292c576d8be3ad (diff) | |
| download | llvm-f66bdb5ea8658fdcbac75f96a73e906f380e5741.zip llvm-f66bdb5ea8658fdcbac75f96a73e906f380e5741.tar.gz llvm-f66bdb5ea8658fdcbac75f96a73e906f380e5741.tar.bz2 | |
AMDGPU/SI: Add llvm.amdgcn.s.waitcnt.all intrinsic
Summary:
So it appears that to guarantee some of the ordering requirements of a GLSL
memoryBarrier() executed in the shader, we need to emit an s_waitcnt.
(We can't use an s_barrier, because memoryBarrier() may appear anywhere in
the shader, in particular it may appear in non-uniform control flow.)
Reviewers: arsenm, mareko, tstellarAMD
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19203
llvm-svn: 267729
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions