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| author | Akshat Oke <Akshat.Oke@amd.com> | 2025-04-08 17:58:48 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-08 17:58:48 +0530 |
| commit | fcaefc2c19ebe037df7115f02abf23f94c07e8cc (patch) | |
| tree | 810c53ffb2d46eb411c6e73929ca44bd7c7baf66 /llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | |
| parent | 79cb6f05da37520949c006e26c5cef1826090d9d (diff) | |
| download | llvm-fcaefc2c19ebe037df7115f02abf23f94c07e8cc.zip llvm-fcaefc2c19ebe037df7115f02abf23f94c07e8cc.tar.gz llvm-fcaefc2c19ebe037df7115f02abf23f94c07e8cc.tar.bz2 | |
[AMDGPU][NPM] Port SIPreEmitPeephole to NPM (#130065)
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f9029d3..c2bcd53 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -542,7 +542,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeSIModeRegisterLegacyPass(*PR); initializeSIWholeQuadModeLegacyPass(*PR); initializeSILowerControlFlowLegacyPass(*PR); - initializeSIPreEmitPeepholePass(*PR); + initializeSIPreEmitPeepholeLegacyPass(*PR); initializeSILateBranchLoweringLegacyPass(*PR); initializeSIMemoryLegalizerLegacyPass(*PR); initializeSIOptimizeExecMaskingLegacyPass(*PR); @@ -2173,9 +2173,8 @@ void AMDGPUCodeGenPassBuilder::addPreEmitPass(AddMachinePass &addPass) const { if (isPassEnabled(EnableSetWavePriority, CodeGenOptLevel::Less)) addPass(AMDGPUSetWavePriorityPass()); - if (TM.getOptLevel() > CodeGenOptLevel::None) { - // TODO: addPass(SIPreEmitPeepholePass()); - } + if (TM.getOptLevel() > CodeGenOptLevel::None) + addPass(SIPreEmitPeepholePass()); // The hazard recognizer that runs as part of the post-ra scheduler does not // guarantee to be able handle all hazards correctly. This is because if there |