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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-07-27 14:31:55 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-07-27 14:31:55 +0000 |
| commit | 6756a2c95335fba8bece4402e62f5057a20f3b4c (patch) | |
| tree | 709ff96a5dff1a43cd8648f7001709782eb47020 /llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | |
| parent | 5e402eec7bc306343cfba703fd4d4acc981b4ead (diff) | |
| download | llvm-6756a2c95335fba8bece4402e62f5057a20f3b4c.zip llvm-6756a2c95335fba8bece4402e62f5057a20f3b4c.tar.gz llvm-6756a2c95335fba8bece4402e62f5057a20f3b4c.tar.bz2 | |
[GlobalISel] Introduce an instruction selector.
And implement it for AArch64, supporting x/w ADD/OR.
Differential Revision: https://reviews.llvm.org/D22373
llvm-svn: 276875
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 9affa2e..c0c69d8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -317,6 +317,7 @@ public: bool addIRTranslator() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; + bool addGlobalInstructionSelect() override; #endif void addFastRegAlloc(FunctionPass *RegAllocPass) override; void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override; @@ -528,6 +529,10 @@ bool GCNPassConfig::addLegalizeMachineIR() { bool GCNPassConfig::addRegBankSelect() { return false; } + +bool GCNPassConfig::addGlobalInstructionSelect() { + return false; +} #endif void GCNPassConfig::addPreRegAlloc() { |