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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-07-13 16:40:25 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-07-13 16:40:25 +0000 |
commit | de950777804d0fb9ce42190e1fe28e28ec033c2b (patch) | |
tree | 4a122ffa5261339ce2e6fa471542c9a38fb76996 /llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp | |
parent | 218b6a2a2ae682f0e2b42a9f76619a382b723430 (diff) | |
download | llvm-de950777804d0fb9ce42190e1fe28e28ec033c2b.zip llvm-de950777804d0fb9ce42190e1fe28e28ec033c2b.tar.gz llvm-de950777804d0fb9ce42190e1fe28e28ec033c2b.tar.bz2 |
AMDGPU: Fix handling of alignment padding in DAG argument lowering
This was completely broken if there was ever a struct argument, as
this information is thrown away during the argument analysis.
The offsets as passed in to LowerFormalArguments are not useful,
as they partially depend on the legalized result register type,
and they don't consider the alignment in the first place.
Ignore the Ins array, and instead figure out from the raw IR type
what we need to do. This seems to fix the padding computation
if the DAG lowering is forced (and stops breaking arguments
following padded arguments if the arguments were only partially
lowered in the IR)
llvm-svn: 337021
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp index 0574c99..13b4b50 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp @@ -24,16 +24,23 @@ AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) : NoSignedZerosFPMath(MF.getTarget().Options.NoSignedZerosFPMath), MemoryBound(false), WaveLimiter(false) { + const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF); + // FIXME: Should initialize KernArgSize based on ExplicitKernelArgOffset, // except reserved size is not correctly aligned. + const Function &F = MF.getFunction(); if (auto *Resolver = MF.getMMI().getResolver()) { if (AMDGPUPerfHintAnalysis *PHA = static_cast<AMDGPUPerfHintAnalysis*>( Resolver->getAnalysisIfAvailable(&AMDGPUPerfHintAnalysisID, true))) { - MemoryBound = PHA->isMemoryBound(&MF.getFunction()); - WaveLimiter = PHA->needsWaveLimiter(&MF.getFunction()); + MemoryBound = PHA->isMemoryBound(&F); + WaveLimiter = PHA->needsWaveLimiter(&F); } } + + CallingConv::ID CC = F.getCallingConv(); + if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) + ExplicitKernArgSize = ST.getExplicitKernArgSize(F, MaxKernArgAlign); } unsigned AMDGPUMachineFunction::allocateLDSGlobal(const DataLayout &DL, |