GlobalISel: mark simple ops legal even on types < 32-bit.

The 32-bit variants of these operations don't depend on the bits not being
operated on, so they also naturally model operations narrower than the actual
register width.

llvm-svn: 279760

1 files changed, 3 insertions, 4 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
index 8ba6933..4e533dd 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -37,11 +37,10 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
   const LLT v2s64 = LLT::vector(2, 64);
 
   for (auto BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
-    for (auto Ty : {s32, s64, v2s32, v4s32, v2s64})
+    // These operations naturally get the right answer when used on
+    // GPR32, even if the actual type is narrower.
+    for (auto Ty : {s1, s8, s16, s32, s64, v2s32, v4s32, v2s64})
       setAction({BinOp, Ty}, Legal);
-
-    for (auto Ty : {s8, s16})
-      setAction({BinOp, Ty}, WidenScalar);
   }
 
   for (auto BinOp : {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_UDIV})