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| author | Tim Northover <tnorthover@apple.com> | 2016-08-04 21:39:49 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2016-08-04 21:39:49 +0000 |
| commit | 61c16142b4d52b0e62db1e39d21093a56cd5f886 (patch) | |
| tree | d0d724026b74e6bbbfd471eb469855271677025a /llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp | |
| parent | 1cfa919b3d796b99a8fe0c3dfeb9999b3f48fd81 (diff) | |
| download | llvm-61c16142b4d52b0e62db1e39d21093a56cd5f886.zip llvm-61c16142b4d52b0e62db1e39d21093a56cd5f886.tar.gz llvm-61c16142b4d52b0e62db1e39d21093a56cd5f886.tar.bz2 | |
GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.
These are the operations that are trivially identical. Division is omitted for
now because you need to use the correct sign/zero extension.
llvm-svn: 277775
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp index c547f7b..02be3bf 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp @@ -34,7 +34,7 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() { const LLT v4s32 = LLT::vector(4, 32); const LLT v2s64 = LLT::vector(2, 64); - for (auto BinOp : {G_ADD, G_SUB, G_AND, G_OR, G_XOR}) { + for (auto BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) { for (auto Ty : {s32, s64, v2s32, v4s32, v2s64}) setAction(BinOp, Ty, Legal); |