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author | hanbeom <kese111@gmail.com> | 2024-08-25 04:30:40 +0900 |
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committer | GitHub <noreply@github.com> | 2024-08-24 20:30:40 +0100 |
commit | 77fccb35ac08f66d52bb152735e27572bf9f3f93 (patch) | |
tree | 3bfbc4c2f163d5b9600120c65085f8a3a165b6e4 /llvm/lib/Support/VirtualFileSystem.cpp | |
parent | 43b88851cefe68645aa59b1fccc8390a8a31f469 (diff) | |
download | llvm-77fccb35ac08f66d52bb152735e27572bf9f3f93.zip llvm-77fccb35ac08f66d52bb152735e27572bf9f3f93.tar.gz llvm-77fccb35ac08f66d52bb152735e27572bf9f3f93.tar.bz2 |
[AArch64] Replace AND with LSL#2 for LDR target (#34101) (#89531)
Currently, process of replacing bitwise operations consisting of
`LSR`/`LSL` with `And` is performed by `DAGCombiner`.
However, in certain cases, the `AND` generated by this process
can be removed.
Consider following case:
```
lsr x8, x8, #56
and x8, x8, #0xfc
ldr w0, [x2, x8]
ret
```
In this case, we can remove the `AND` by changing the target of `LDR`
to `[X2, X8, LSL #2]` and right-shifting amount change to 56 to 58.
after changed:
```
lsr x8, x8, #58
ldr w0, [x2, x8, lsl #2]
ret
```
This patch checks to see if the `SHIFTING` + `AND` operation on load
target can be optimized and optimizes it if it can.
Diffstat (limited to 'llvm/lib/Support/VirtualFileSystem.cpp')
0 files changed, 0 insertions, 0 deletions