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| author | Huihui Zhang <huihuiz@quicinc.com> | 2021-06-14 16:21:24 -0700 |
|---|---|---|
| committer | Huihui Zhang <huihuiz@quicinc.com> | 2021-06-14 16:42:34 -0700 |
| commit | 1c096bf09ffd3d51665b60942d6bde19e7dbbd5a (patch) | |
| tree | 778dabdc200e3e1b8ebc3c364620133a95d928c4 /llvm/lib/Support/Timer.cpp | |
| parent | 7a7c00761f6294dc21c40cbe1737354e655cda9b (diff) | |
| download | llvm-1c096bf09ffd3d51665b60942d6bde19e7dbbd5a.zip llvm-1c096bf09ffd3d51665b60942d6bde19e7dbbd5a.tar.gz llvm-1c096bf09ffd3d51665b60942d6bde19e7dbbd5a.tar.bz2 | |
[SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE.
Currently, Loop strengh reduce is not handling loops with scalable stride very well.
Take loop vectorized with scalable vector type <vscale x 8 x i16> for instance,
(refer to test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll added).
Memory accesses are incremented by "16*vscale", while induction variable is incremented
by "8*vscale". The scaling factor "2" needs to be extracted to build candidate formula
i.e., "reg(%in) + 2*reg({0,+,(8 * %vscale)}". So that addrec register reg({0,+,(8*vscale)})
can be reused among Address and ICmpZero LSRUses to enable optimal solution selection.
This patch allow LSR getExactSDiv to recognize special cases like "C1*X*Y /s C2*X*Y",
and pull out "C1 /s C2" as scaling factor whenever possible. Without this change, LSR
is missing candidate formula with proper scaled factor to leverage target scaled-index
addressing mode.
Note: This patch doesn't fully fix AArch64 isLegalAddressingMode for scalable
vector. But allow simple valid scale to pass through.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D103939
Diffstat (limited to 'llvm/lib/Support/Timer.cpp')
0 files changed, 0 insertions, 0 deletions