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| author | Pavel Iliin <Pavel.Iliin@arm.com> | 2020-02-04 14:51:17 +0000 |
|---|---|---|
| committer | Pavel Iliin <Pavel.Iliin@arm.com> | 2020-02-14 14:19:39 +0000 |
| commit | b6a9fe209992789be3ed95664d25196361cfad34 (patch) | |
| tree | 824beb442c33f9bbe45fb463b452ef262fe4af30 /llvm/lib/Support/ThreadPool.cpp | |
| parent | 1d40c4150630729a9c1ce5119a8027dac93a5b2d (diff) | |
| download | llvm-b6a9fe209992789be3ed95664d25196361cfad34.zip llvm-b6a9fe209992789be3ed95664d25196361cfad34.tar.gz llvm-b6a9fe209992789be3ed95664d25196361cfad34.tar.bz2 | |
[AArch64] Add BIT/BIF support.
This patch added generation of SIMD bitwise insert BIT/BIF instructions.
In the absence of GCC-like functionality for optimal constraints satisfaction
during register allocation the bitwise insert and select patterns are matched
by pseudo bitwise select BSP instruction with not tied def.
It is expanded later after register allocation with def tied
to BSL/BIT/BIF depending on operands registers.
This allows to get rid of redundant moves.
Reviewers: t.p.northover, samparker, dmgreen
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D74147
Diffstat (limited to 'llvm/lib/Support/ThreadPool.cpp')
0 files changed, 0 insertions, 0 deletions