diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-11-27 10:41:32 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-11-27 10:41:32 +0000 |
| commit | 97160be53d46833b38b1d9310a9800fe85f83055 (patch) | |
| tree | 8e45cfb824eb684eadff236f07f420c2a8c46345 /llvm/lib/Support/ThreadPool.cpp | |
| parent | 60ccb7daf14df2da16511cd443028038d0843143 (diff) | |
| download | llvm-97160be53d46833b38b1d9310a9800fe85f83055.zip llvm-97160be53d46833b38b1d9310a9800fe85f83055.tar.gz llvm-97160be53d46833b38b1d9310a9800fe85f83055.tar.bz2 | |
[X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule class
As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general).
Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes.
Differential Revision: https://reviews.llvm.org/D40351
llvm-svn: 319016
Diffstat (limited to 'llvm/lib/Support/ThreadPool.cpp')
0 files changed, 0 insertions, 0 deletions