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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-04-07 09:32:51 -0400 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-04-14 22:05:22 -0400 |
| commit | cb5dc3765bddc4e6bcd92e588c33cfa8424eb437 (patch) | |
| tree | 7750872ce8ecac9da7838b1b732d566258e0a108 /llvm/lib/Support/StringExtras.cpp | |
| parent | 229e392b4edb65b69caa49644cdeaa358095146d (diff) | |
| download | llvm-cb5dc3765bddc4e6bcd92e588c33cfa8424eb437.zip llvm-cb5dc3765bddc4e6bcd92e588c33cfa8424eb437.tar.gz llvm-cb5dc3765bddc4e6bcd92e588c33cfa8424eb437.tar.bz2 | |
TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands
This was hitting the default instruction constraint code which uses
the register classes in the instruction def, which REG_SEQUENCE does
not have.
Fixes not constraining the register class for AMDGPU fneg/fabs
patterns, which would fail when the use was another generic,
unconstrained instruction.
Another oddity I noticed is that the temporary registers are created
with an unnecessary, but incorrect 16-bit LLT but this shouldn't
matter.
I'm also still unclear why root and sub-instructions have to be
handled differently.
Diffstat (limited to 'llvm/lib/Support/StringExtras.cpp')
0 files changed, 0 insertions, 0 deletions