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author | Tony <Tony.Tye@amd.com> | 2020-02-20 02:08:59 -0500 |
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committer | Tony <Tony.Tye@amd.com> | 2020-04-14 20:05:15 -0400 |
commit | b43612401077912a577fd9700c7284b6e676f3fe (patch) | |
tree | b84cc753b0444400dfed079f8df070683c533600 /llvm/lib/Support/StringExtras.cpp | |
parent | 1cd92e480c12c03ab9a381b29e4e3964892afa01 (diff) | |
download | llvm-b43612401077912a577fd9700c7284b6e676f3fe.zip llvm-b43612401077912a577fd9700c7284b6e676f3fe.tar.gz llvm-b43612401077912a577fd9700c7284b6e676f3fe.tar.bz2 |
[AMDGPU] Update DWARF proposal
- Unify the sections on DWARF expression and location lists.
- Allow a location description to have one or more single location
descriptions.
- Define context of DWARF expression that includes an initial
stack. Allow initial stack to be used when evaluating location list
expression with overlapping PC ranges.
- Reorganize the DWARF proposal in AMDGPUUsage so suitable for
submission to the DWARF site.
- Replace CFI instruction DW_CFA_LLVM_def_cfa_aspace with
DW_CFA_def_aspace_cfa and DW_CFA_def_aspace_cfa_sf. This is to avoid
the problem that DW_CFA_def_cfa and DW_CFA_def_cfa_sf cannot use a
register that is not the size of an address in the CFA address
space.
- Clarify DWARF address class and DWARF address space. Define language
values for DWARF address classes and specify how they are used by
some common source languages.
- Define rules for accessing registers and derefencing memory when the
type size and register size or byte size operand do not match.
- Numerous cleanups for consistency.
Differential Revision: https://reviews.llvm.org/D70523
Diffstat (limited to 'llvm/lib/Support/StringExtras.cpp')
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