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| author | Craig Topper <craig.topper@sifive.com> | 2021-04-08 09:12:57 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-04-08 11:34:56 -0700 |
| commit | 02ef9963e1ad1e6ded539c830861a074b879dc70 (patch) | |
| tree | 246ab3f06ceff1af07975a91c6ca73bff65d7afd /llvm/lib/Support/Signposts.cpp | |
| parent | 5f0ac1ef78880f233dea2070ab55894c6bd2690c (diff) | |
| download | llvm-02ef9963e1ad1e6ded539c830861a074b879dc70.zip llvm-02ef9963e1ad1e6ded539c830861a074b879dc70.tar.gz llvm-02ef9963e1ad1e6ded539c830861a074b879dc70.tar.bz2 | |
[RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.
The backend can't handle this and will throw a fatal error from
type legalization. It's easy enough to fix that for this intrinsic
by just splitting the IR intrinsic since it works on individual bytes.
There will be other intrinsics in the future that would be harder
to support through splitting, for example grev, gorc, and shfl. Those
would require a compare and a select be inserted to check the MSB of
their control input.
This patch adds support for preventing this in the frontend with
a nice diagnostic.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D99984
Diffstat (limited to 'llvm/lib/Support/Signposts.cpp')
0 files changed, 0 insertions, 0 deletions