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| author | Craig Topper <craig.topper@sifive.com> | 2021-01-13 17:14:45 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-01-13 17:14:49 -0800 |
| commit | dfc1901d513e1c5b9472d9b3403ca991b3d4a232 (patch) | |
| tree | d17fd115d40681b925e47968ebe57e10bdd5c676 /llvm/lib/Support/Program.cpp | |
| parent | 3de92ca78cd4e180920acc077452f87c44c7d935 (diff) | |
| download | llvm-dfc1901d513e1c5b9472d9b3403ca991b3d4a232.zip llvm-dfc1901d513e1c5b9472d9b3403ca991b3d4a232.tar.gz llvm-dfc1901d513e1c5b9472d9b3403ca991b3d4a232.tar.bz2 | |
[RISCV] Custom lower ISD::VSCALE.
This patch custom lowers ISD::VSCALE into a csrr vlenb followed
by a shift right by 3 followed by a multiply by the scale amount.
I've added computeKnownBits support to indicate that the csrr vlenb
always produces 3 trailng bits of 0s so the shift right is "exact".
This allows the shift and multiply sequence to be nicely optimized
into a single shift or removed completely when the scale amount is
a power of 2.
The non power of 2 case multiplying by 24 is still producing
suboptimal code. We could remove the right shift and use a
multiply by 3. Hopefully we can improve DAG combine to fix that
since it's not unique to this sequence.
This replaces D94144.
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D94249
Diffstat (limited to 'llvm/lib/Support/Program.cpp')
0 files changed, 0 insertions, 0 deletions