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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-11 15:16:15 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-11 15:16:15 +0000 |
| commit | 032a01f74acf5728c024e42ce991c0a34492f32c (patch) | |
| tree | 84257cad3bbbe601384fe7f10dad21e71aeb3a25 /llvm/lib/Support/Parallel.cpp | |
| parent | 868b31bf21b0400383f198b84ddefc6fdc5e6c4a (diff) | |
| download | llvm-032a01f74acf5728c024e42ce991c0a34492f32c.zip llvm-032a01f74acf5728c024e42ce991c0a34492f32c.tar.gz llvm-032a01f74acf5728c024e42ce991c0a34492f32c.tar.bz2 | |
[X86][SLM] Vector stores only use the MEC port.
Confirmed by both Agner and Intel's AOM - the IEC/FPC are not required for pure load/stores (even if its a partial update).
Can't fix WriteStore until all RMW instructions are cleaned up though....
llvm-svn: 332096
Diffstat (limited to 'llvm/lib/Support/Parallel.cpp')
0 files changed, 0 insertions, 0 deletions